-- comf.include: UQDS_specifics_pkg.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library uqdslib;
use uqdslib.UQDS_Specifics_pkg.all;

entity spi_master_tb is
end;

architecture bench of spi_master_tb is
  -- Clock period
  constant clk_period : time := 5 ns;
  -- Generics
  constant clkdiv : integer := 40;
  constant clk_idle : std_logic := '1';

  -- Ports
  signal rst : std_logic := '0';
  signal clk : std_logic;
  signal data_tx : std_logic_vector(7 downto 0);
  signal data_rx : std_logic_vector(7 downto 0);
  signal send_request : std_logic;
  signal byte_tx_complete : std_logic;
  signal byte_rx_complete : std_logic;
  signal pin_mosi : std_logic;
  signal pin_miso : std_logic;
  signal pin_clk : std_logic;

    signal test_done : std_logic := '0';

begin

  spi_master_inst : uqdslib.UQDS_Specifics_pkg.spi_master
    generic map (
      clkdiv => clkdiv,
      clk_idle => clk_idle
    )
    port map (
      rst => rst,
      clk => clk,
      spi_control_to.data_tx => data_tx,
      spi_control_to.send_request => send_request,
      spi_control_from.data_rx => data_rx,
      spi_control_from.byte_tx_complete => byte_tx_complete,
      spi_control_from.byte_rx_complete => byte_rx_complete,
      pin_mosi => pin_mosi,
      pin_miso => pin_miso,
      pin_clk => pin_clk
    );

    pin_miso <= pin_mosi;

  clk_process : process
  begin
    clk <= '1';
    wait for clk_period/2;
    clk <= '0';
    wait for clk_period/2;

    if(test_done) then wait; end if;
  end process clk_process;

  data_process : process
  begin

    rst <= '1';
    wait for 100 ns;
    rst <= '0';

    for i in 0 to 4 loop
        data_tx <= std_logic_vector(to_unsigned(i, data_tx'length));
        send_request <= '1';
        wait until falling_edge(byte_tx_complete) for 1 ms;
        send_request <= '0';
    end loop;

    for i in 0 to 4 loop
        data_tx <= std_logic_vector(to_unsigned(i, data_tx'length));
        send_request <= '1';
        wait until falling_edge(byte_tx_complete) for 1 ms;
        send_request <= '0';

        wait for 1.5 us;
    end loop;

    data_tx <= std_logic_vector(to_unsigned(69, data_tx'length));
    send_request <= '1';
    wait until falling_edge(byte_tx_complete) for 1 ms;
    send_request <= '0';

    wait for 400 ns;
    rst <= '1';
    wait for 100 ns;
    rst <= '0';
    wait for 3 us;

    test_done <= '1';

    wait until falling_edge(byte_rx_complete) for 1 us;

    wait;

  end process data_process;
end;