-- ! @author David Bailey (d.bailey@cern.ch)

-- comf.reference: spi_master.vhd
-- comf.vhdl.work: uqdslib

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

package UQDS_specifics_pkg is
    type spi_control_to_t is record
        --! Byte to be sent out through the SPI MOSI pin.
        --! Data is latched when send_request is 1 AND SPI port is idle.
        --! When the data is latched, byte_complete goes 1 for 1 clk tick
        data_tx : std_logic_vector(7 downto 0);
    
        --! Hold high to request another byte to be sent out.
        --! Once the byte has been latched, byte_complete will go high
        --! for one clk. The code may then prepare the next byte to 
        --! be sent out.
        send_request : std_logic;
    end record spi_control_to_t;

    type spi_control_from_t is record
        --! Byte that was received from the MISO pin. Latched in with together
        --! with the byte_complete signal. Valid for the entire byte.
        data_rx : std_logic_vector(7 downto 0);

        --! High for one clk whenever a SPI transaction has occured.
        --! This signal has two functons:
        --! 1. The data_tx byte has been latched, next byte may be prepared
        byte_tx_complete : std_logic;
        byte_rx_complete : std_logic;
    end record spi_control_from_t;

    component uart_simple_rx is 
    generic (
        --! Baudrate clock divider. Set to `clk / baudrate`
        baud_clk_div : natural := 40000;
        --! Internal value, do not modify
        baud_clk_div_max : natural := baud_clk_div*3/2
    );
    port (
        --! Active-high, synchronous reset
        rst : in std_logic;
        --! Main clock input
        clk : in std_logic;

        --! UART RX IO Pin
        pin_rx : in std_logic;

        --! Last fully captured byte of data, valid
        --! on the same clk cycle that `data_rx_pulse` goes high
        data_rx : out unsigned(7 downto 0);
        --! Pulsed for one clk cycle to indicate reception of a new byte
        data_rx_pulse : out std_logic
    );
    end component;

    type uqds_powersupply_data_t is record
        temperature_k  : integer;
        voltage_5V_mv  : integer;
        voltage_5V0_mv : integer;
        voltage_15V_mv : integer;
    end record uqds_powersupply_data_t;

    type uqds_powersupply_data_array_t is array (natural range <>) of uqds_powersupply_data_t;

    component powersupply_monitor
    generic (
        --! Clock divider for the device timeout generation.
        device_timeout_clkdiv : natural := 500 * 40000;
        --! Clock divider for the UART packet reset. Set to approx.
        --! twice the clock cycles of one byte transmission.
        uart_rx_timeout_clkdiv   : natural := 30 * 40000
    );
    port (
        --! Synchronous reset
        rst : in std_logic;
        --! Clock, rising edge logic
        clk : in std_logic;

        --! Connect to UART RX module
        uart_data_rx : in unsigned(7 downto 0);
        uart_data_rx_pulse : in std_logic;

        --! Array of pre-converted measurements. Zeroed upon
        --! device timeout
        measurements : out uqds_powersupply_data_t;
        --! '1' as long as valid data is being received from the 
        --! power supply
        psu_ok : out std_logic
    );
    end component;

	
	component powersupply_monitor_top
		 generic (
        --! Number of PSUs to instantiate
        psu_count : positive := 2;
        --! Clock divider for the UART Baudrate
        psu_uart_clkdiv : natural := 1 * 40000;
        --! Clock divider for the timeout of the PSU.
        --! Once timed out, the device will be assumed nonfunctional
        psu_timeout_clkdiv : natural := 500 * 40000
    );
    port (
        rst : in std_logic;
        clk : in std_logic;

        pins_uart_rx : in std_logic_vector(psu_count-1 downto 0);

        --! Array of PSU measurements. Each power supply reports on its temperature,
        --! internal and external 5V levels, and 15V level.
        --! If the PSU is offline, these values will be reset to zero for the 
        --! respective power supply.
        psu_measurements : out uqds_powersupply_data_array_t(psu_count-1 downto 0)
    );
	end component;

    component spi_master
    generic (
        clkdiv : natural := 400;
        clk_idle : std_logic := '1'
    );
        port (
        rst : in std_logic;
        clk : in std_logic;

        spi_control_to : in spi_control_to_t;
        spi_control_from : out spi_control_from_t;

        pin_mosi : out std_logic;
        pin_miso : in std_logic;
        pin_clk : out std_logic
    );
    end component;
end package;