108 lines
2.4 KiB
VHDL
108 lines
2.4 KiB
VHDL
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-- comf.include: UQDS_specifics_pkg.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library uqdslib;
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use uqdslib.UQDS_Specifics_pkg.all;
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entity spi_master_tb is
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end;
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architecture bench of spi_master_tb is
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-- Clock period
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constant clk_period : time := 5 ns;
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-- Generics
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constant clkdiv : integer := 40;
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constant clk_idle : std_logic := '1';
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-- Ports
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signal rst : std_logic := '0';
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signal clk : std_logic;
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signal data_tx : std_logic_vector(7 downto 0);
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signal data_rx : std_logic_vector(7 downto 0);
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signal send_request : std_logic;
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signal byte_tx_complete : std_logic;
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signal byte_rx_complete : std_logic;
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signal pin_mosi : std_logic;
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signal pin_miso : std_logic;
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signal pin_clk : std_logic;
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signal test_done : std_logic := '0';
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begin
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spi_master_inst : uqdslib.UQDS_Specifics_pkg.spi_master
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generic map (
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clkdiv => clkdiv,
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clk_idle => clk_idle
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)
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port map (
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rst => rst,
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clk => clk,
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spi_control_to.data_tx => data_tx,
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spi_control_to.send_request => send_request,
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spi_control_from.data_rx => data_rx,
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spi_control_from.byte_tx_complete => byte_tx_complete,
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spi_control_from.byte_rx_complete => byte_rx_complete,
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pin_mosi => pin_mosi,
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pin_miso => pin_miso,
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pin_clk => pin_clk
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);
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pin_miso <= pin_mosi;
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clk_process : process
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begin
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clk <= '1';
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wait for clk_period/2;
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clk <= '0';
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wait for clk_period/2;
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if(test_done) then wait; end if;
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end process clk_process;
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data_process : process
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begin
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rst <= '1';
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wait for 100 ns;
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rst <= '0';
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for i in 0 to 4 loop
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data_tx <= std_logic_vector(to_unsigned(i, data_tx'length));
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send_request <= '1';
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wait until falling_edge(byte_tx_complete) for 1 ms;
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send_request <= '0';
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end loop;
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for i in 0 to 4 loop
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data_tx <= std_logic_vector(to_unsigned(i, data_tx'length));
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send_request <= '1';
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wait until falling_edge(byte_tx_complete) for 1 ms;
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send_request <= '0';
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wait for 1.5 us;
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end loop;
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data_tx <= std_logic_vector(to_unsigned(69, data_tx'length));
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send_request <= '1';
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wait until falling_edge(byte_tx_complete) for 1 ms;
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send_request <= '0';
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wait for 400 ns;
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rst <= '1';
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wait for 100 ns;
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rst <= '0';
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wait for 3 us;
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test_done <= '1';
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wait until falling_edge(byte_rx_complete) for 1 us;
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wait;
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end process data_process;
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end;
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