138 lines
No EOL
4.5 KiB
VHDL
138 lines
No EOL
4.5 KiB
VHDL
-- ! @author David Bailey (d.bailey@cern.ch)
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-- comf.reference: spi_master.vhd
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-- comf.vhdl.work: uqdslib
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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package UQDS_specifics_pkg is
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type spi_control_to_t is record
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--! Byte to be sent out through the SPI MOSI pin.
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--! Data is latched when send_request is 1 AND SPI port is idle.
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--! When the data is latched, byte_complete goes 1 for 1 clk tick
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data_tx : std_logic_vector(7 downto 0);
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--! Hold high to request another byte to be sent out.
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--! Once the byte has been latched, byte_complete will go high
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--! for one clk. The code may then prepare the next byte to
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--! be sent out.
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send_request : std_logic;
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end record spi_control_to_t;
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type spi_control_from_t is record
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--! Byte that was received from the MISO pin. Latched in with together
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--! with the byte_complete signal. Valid for the entire byte.
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data_rx : std_logic_vector(7 downto 0);
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--! High for one clk whenever a SPI transaction has occured.
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--! This signal has two functons:
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--! 1. The data_tx byte has been latched, next byte may be prepared
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byte_tx_complete : std_logic;
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byte_rx_complete : std_logic;
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end record spi_control_from_t;
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component uart_simple_rx is
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generic (
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--! Baudrate clock divider. Set to `clk / baudrate`
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baud_clk_div : natural := 40000;
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--! Internal value, do not modify
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baud_clk_div_max : natural := baud_clk_div*3/2
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);
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port (
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--! Active-high, synchronous reset
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rst : in std_logic;
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--! Main clock input
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clk : in std_logic;
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--! UART RX IO Pin
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pin_rx : in std_logic;
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--! Last fully captured byte of data, valid
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--! on the same clk cycle that `data_rx_pulse` goes high
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data_rx : out unsigned(7 downto 0);
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--! Pulsed for one clk cycle to indicate reception of a new byte
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data_rx_pulse : out std_logic
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);
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end component;
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type uqds_powersupply_data_t is record
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temperature_k : integer;
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voltage_5V_mv : integer;
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voltage_5V0_mv : integer;
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voltage_15V_mv : integer;
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end record uqds_powersupply_data_t;
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type uqds_powersupply_data_array_t is array (natural range <>) of uqds_powersupply_data_t;
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component powersupply_monitor
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generic (
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--! Clock divider for the device timeout generation.
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device_timeout_clkdiv : natural := 500 * 40000;
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--! Clock divider for the UART packet reset. Set to approx.
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--! twice the clock cycles of one byte transmission.
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uart_rx_timeout_clkdiv : natural := 30 * 40000
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);
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port (
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--! Synchronous reset
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rst : in std_logic;
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--! Clock, rising edge logic
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clk : in std_logic;
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--! Connect to UART RX module
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uart_data_rx : in unsigned(7 downto 0);
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uart_data_rx_pulse : in std_logic;
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--! Array of pre-converted measurements. Zeroed upon
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--! device timeout
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measurements : out uqds_powersupply_data_t;
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--! '1' as long as valid data is being received from the
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--! power supply
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psu_ok : out std_logic
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);
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end component;
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component powersupply_monitor_top
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generic (
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--! Number of PSUs to instantiate
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psu_count : positive := 2;
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--! Clock divider for the UART Baudrate
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psu_uart_clkdiv : natural := 1 * 40000;
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--! Clock divider for the timeout of the PSU.
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--! Once timed out, the device will be assumed nonfunctional
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psu_timeout_clkdiv : natural := 500 * 40000
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);
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port (
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rst : in std_logic;
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clk : in std_logic;
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pins_uart_rx : in std_logic_vector(psu_count-1 downto 0);
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--! Array of PSU measurements. Each power supply reports on its temperature,
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--! internal and external 5V levels, and 15V level.
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--! If the PSU is offline, these values will be reset to zero for the
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--! respective power supply.
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psu_measurements : out uqds_powersupply_data_array_t(psu_count-1 downto 0)
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);
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end component;
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component spi_master
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generic (
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clkdiv : natural := 400;
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clk_idle : std_logic := '1'
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);
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port (
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rst : in std_logic;
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clk : in std_logic;
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spi_control_to : in spi_control_to_t;
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spi_control_from : out spi_control_from_t;
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pin_mosi : out std_logic;
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pin_miso : in std_logic;
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pin_clk : out std_logic
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);
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end component;
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end package; |